Test method and test apparatus for testing a plurality of blocks in a circuit

ABSTRACT

A test apparatus and a test method for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures. The test apparatus includes a comparing device, configured to collect output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel, compare the output responses of the plurality of blocks to determine whether the output responses of the plurality of blocks are identical, and output results of the comparison of the comparing device; and a determining device, configured to receive the results of the comparison of the comparing device, and determine whether the plurality of blocks have a defect according to the results of the comparison of the comparing device.

BACKGROUND

The present disclosure relates to a field of design for testability of acircuit (e.g., a chip), and more specifically, to a test method and atest apparatus for testing a plurality of blocks in a circuit, theplurality of blocks having identical structures.

In order to improve circuit test efficiency, a hardware logic which maybe used for testing a circuit is added into the circuit at a stage ofdesigning the circuit, which is known as Design for Testability (DFT) ofthe circuit. Currently, a prevailing DFT method is a scan-based testmethod, which aims at identifying a manufacturing defect of a circuit(e.g., an undesirable short circuit or open circuit, etc.), rather thanverifying a function of the circuit. In this method, when the circuit isdesigned, registers in the circuit are replaced with scan registershaving scan input ports and scan output ports. When the circuit istested, all the scan registers in the circuit may be connected into ascan chain. Then, excitation signals corresponding to one or more testpatterns generated by an Automatic Test Pattern Generation (ATPG) toolare input to the scan chain, respectively. As known in the art, eachtest pattern can be used for testing, for example, one type of circuitdefect, and includes an excitation signal to be applied to a circuit andan expected output response that should be generated in response toapplication of the excitation signal. Thus, by determining whetheroutput responses of the scan chain are consistent with expected outputresponses corresponding to the respective test patterns, it can bedetermined whether the circuit has corresponding defects.

A plurality of blocks having identical structures (also referred to asreused blocks), such as intellectual property (IP) cores, neuron blocksin a cognitive computing circuit, etc., are often used in a designedcircuit. As a scale of the circuit increases, a number of the blockshaving the identical structures used in the circuit also increases. Inexisting DFT methods, these blocks are treated in the same way as otherblocks, instead of adjusting the test methods for the circuit accordingto characteristics (i.e., “identical”) of these blocks, therefore testefficiency is not high.

SUMMARY

Embodiments of the present disclosure provide a test apparatus and atest method for testing a plurality of blocks having identicalstructures in a circuit, which can simplify a test process for theplurality of blocks having the identical structures and improve testefficiency.

According to an aspect of the present disclosure, there is provided atest apparatus for testing a plurality of blocks in a circuit, theplurality of blocks having identical structures, the test apparatuscomprising: a comparing device, configured to collect output responsesgenerated by the plurality of blocks by applying an excitation signal tothe plurality of blocks in parallel, compare the output responses of theplurality of blocks to determine whether the output responses of theplurality of blocks are identical, and output results of the comparisonof the comparing device; and a determining device, configured to receivethe results of the comparison, and determine whether the plurality ofblocks have a defect according to the results of the comparison of thecomparing device.

According to another aspect of the present disclosure, there is provideda test method for testing a plurality of blocks in a circuit, theplurality of blocks having identical structures, the test methodcomprising: collecting output responses generated by the plurality ofblocks by applying an excitation signal to the plurality of blocks inparallel; comparing the output responses of the plurality of blocks todetermine whether the output responses of the plurality of blocks areidentical; and determining whether the plurality of blocks have a defectaccording to results of the comparison.

According to yet another aspect of the present disclosure, there isprovided a test apparatus for testing a plurality of blocks in acircuit, the plurality of blocks having identical structures, and thetest apparatus may execute the test method according to the above aspectof the present disclosure.

With the test apparatus and the test method according to the aboveaspects of the present disclosure, when a circuit includes a pluralityof blocks having identical structures, an excitation signal can beapplied to the respective blocks in parallel, and it can be determinedwhether these blocks have a defect according to output responses of therespective blocks. Thus, the plurality of blocks can be tested inparallel so that test efficiency may be improved. In addition, since theplurality of blocks can share one or more test patterns, the testapparatus and the test method described above can simplify a testprocess for the blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

Through the more detailed description of some embodiments of the presentdisclosure in the accompanying drawings, the above and other objects,features and advantages of the present disclosure will become moreapparent, wherein the same reference generally refers to the samecomponents in the embodiments of the present disclosure.

FIG. 1 shows an exemplary computer system/server 12 which is applicableto implement the embodiments of the present disclosure;

FIG. 2 shows a schematic diagram of connecting scan registers of each ofsix blocks having identical structures into one scan chain;

FIG. 3 shows a block diagram of a test apparatus for testing a pluralityof blocks having identical structures in a circuit according to anembodiment of the present disclosure;

FIG. 4 shows an exemplary implementation of the test apparatus fortesting a plurality of blocks having identical structures in a circuitaccording to the embodiment of the present disclosure;

FIG. 5 shows an example of a method by which a determining device shownin FIG. 3 determines a block having a defect;

FIG. 6 shows a flow chart of a test method for testing a plurality ofblocks having identical structures in a circuit according to anembodiment of the present disclosure; and

FIG. 7 shows a block diagram of a test apparatus for testing a pluralityof blocks having identical structures in a circuit according to anotherembodiment of the present disclosure.

DETAILED DESCRIPTION

Some preferable embodiments will be described in more detail withreference to the accompanying drawings, in which the preferableembodiments of the present disclosure have been illustrated. However,the present disclosure can be implemented in various manners, and thusshould not be construed to be limited to the embodiments disclosedherein. On the contrary, those embodiments are provided for the thoroughand complete understanding of the present disclosure, and completelyconveying the scope of the present disclosure to those skilled in theart.

Referring now to FIG. 1, in which an exemplary computer system/server 12which is applicable to implement the embodiments of the presentinvention is shown. Computer system/server 12 is only illustrative andis not intended to suggest any limitation as to the scope of use orfunctionality of embodiments of the invention described herein.

As shown in FIG. 1, computer system/server 12 is shown in the form of ageneral-purpose computing device. The components of computersystem/server 12 may include, but are not limited to, one or moreprocessors or processing units 16, a system memory 28, and a bus 18 thatcouples various system components including system memory 28 toprocessor 16.

Bus 18 represents one or more of any of several types of bus structures,including a memory bus or memory controller, a peripheral bus, anaccelerated graphics port, and a processor or local bus using any of avariety of bus architectures. By way of example, and not limitation,such architectures include Industry Standard Architecture (ISA) bus,Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, VideoElectronics Standards Association (VESA) local bus, and PeripheralComponent Interconnect (PCI) bus.

Computer system/server 12 typically includes a variety of computersystem readable media. Such media may be any available media that isaccessible by computer system/server 12, and it includes both volatileand non-volatile media, removable and non-removable media.

System memory 28 can include computer system readable media in the formof volatile memory, such as random access memory (RAM) 30 and/or cachememory 32. Computer system/server 12 may further include otherremovable/non-removable, volatile/non-volatile computer system storagemedia. By way of example only, storage system 34 can be provided forreading from and writing to a non-removable, non-volatile magnetic media(not shown and typically called a “hard drive”). Although not shown, amagnetic disk drive for reading from and writing to a removable,non-volatile magnetic disk (e.g., a “floppy disk”), and an optical diskdrive for reading from or writing to a removable, non-volatile opticaldisk such as a CD-ROM, DVD-ROM or other optical media can be provided.In such instances, each can be connected to bus 18 by one or more datamedia interfaces. As will be further depicted and described below,memory 28 may include at least one program product having a set (e.g.,at least one) of program modules that are configured to carry out thefunctions of embodiments of the invention.

Program/utility 40, having a set (at least one) of program modules 42,may be stored in memory 28 by way of example, and not limitation, aswell as an operating system, one or more application programs, otherprogram modules, and program data. Each of the operating system, one ormore application programs, other program modules, and program data orsome combination thereof, may include an implementation of a networkingenvironment. Program modules 42 generally carry out the functions and/ormethodologies of embodiments of the invention as described herein.

Computer system/server 12 may also communicate with one or more externaldevices 14 such as a keyboard, a pointing device, a display 24, etc.;one or more devices that enable a user to interact with computersystem/server 12; and/or any devices (e.g., network card, modem, etc.)that enable computer system/server 12 to communicate with one or moreother computing devices. Such communication can occur via Input/Output(I/O) interfaces 22. Still yet, computer system/server 12 cancommunicate with one or more networks such as a local area network(LAN), a general wide area network (WAN), and/or a public network (e.g.,the Internet) via network adapter 20. As depicted, network adapter 20communicates with the other components of computer system/server 12 viabus 18. It should be understood that although not shown, other hardwareand/or software components could be used in conjunction with computersystem/server 12. Examples, include, but are not limited to: microcode,device drivers, redundant processing units, external disk drive arrays,RAID systems, tape drives, and data archival storage systems, etc.

With reference now to the accompanying drawings, a test apparatus and atest method for testing a plurality of blocks having identicalstructures in a circuit according to embodiments of the presentdisclosure will be described in detail. The circuit described herein maybe a circuit in any form, such as an integrated circuit (or a chip) or anon-integrated circuit (or a discrete-component circuit). Hereinafter,the embodiments of the present disclosure will be described by using achip as an example, and the description is also applicable to circuitsin other forms.

In the embodiment of the present disclosure, the plurality of blockshaving the identical structures in the chip (which sometimes may besimply referred to as blocks hereinafter for convenience of description)have identical scan structures. As known in the art, a scan structure ofa block refers to a number(s) and a construction(s) of a scan chain(s)included in the block, where a construction of a scan chain may includea scan register(s) connected in the scan chain and a connection order ofthe scan register(s). Specifically, as described above, when the chip isdesigned, the registers (including the registers in the respectiveblocks) in the chip may be replaced with scan registers having scaninput (SI) ports and scan output (SO) ports, and accordingly, a SI portand a SO port may be provided on the chip, so as to receive scan/enablesignals from outside and to output a test result to outside, etc. duringthe test. Each scan register can be switched between a scan mode and anormal mode (i.e., a register mode). Specifically, when the chip isused, the respective scan registers are kept in the normal mode, so thatthe respective scan registers execute a registering operation. When thechip is tested, the respective scan registers are switched to the scanmode to perform a scan test. In the embodiment of the presentdisclosure, the scan registers in each block may be connected into oneor more scan chains, so that numbers of the scan chains in differentblocks are the same, and constructions of the corresponding scan chainsin different blocks are also the same, i.e., the respective blocks havea same scan structure. In other words, the respective blocks have thescan chains with identical structures. FIG. 2 shows a schematic diagramof connecting scan registers of each of six blocks having identicalstructures into one scan chain. In the example shown in FIG. 2, numbers(1) and constructions of the scan chains in blocks 201-206 areidentical, so these blocks have the scan chains with identicalstructures or have identical scan structures. Additionally, as shown inFIG. 2, each scan chain has an input port and an output port. The inputports of the scan chains of the respective blocks may be connectedtogether, so that an excitation signal may be input in parallel (i.e.,broadcast) to the respective blocks via the input ports. It is to berecognized that, although FIG. 2 shows six blocks having the identicalstructures, this is only exemplary, and the number of the blocks mayvary according to actual design requirements. Furthermore, although thescan registers in each block can be connected into one or more scanchains, the embodiments of the present disclosure will be describedhereinafter by using one scan chain as an example for convenience ofdescription.

To test the respective blocks, one or more test patterns can begenerated in advance by using an ATPG tool based on netlists of theblocks. As described above, each test pattern includes an excitationsignal to be applied to the blocks and an expected output response thatshould be generated by the blocks in response to application of theexcitation signal. At the time of test, the excitation signalcorresponding to each test pattern may be input to the respective blocksin parallel. Thereby, a logical structure test may be performed on therespective blocks, so that the respective blocks generate correspondingoutput responses. The output responses may be signals in various forms,for example, a bit sequence of one or more bits consisting of 0and/or 1. In a case where the chip/block is tested by an Automatic TestApparatus (ATE), the excitation signal may be applied by the ATE. In acase where a Built-in Self-test (BIST) circuit is provided in advance inthe chip, the excitation signal can be applied by the BIST circuit. Amethod for generating the test pattern by the ATPG tool and applying theexcitation signal to the blocks so as to perform the logical structuretest on the respective blocks is known in the art, and a descriptionthereof is omitted here.

In the embodiment of the present disclosure, for each test pattern, itmay be determined whether these blocks have a defect corresponding tothe test pattern according to whether the output responses of theplurality of blocks having the identical structures are the same.Specifically, because the respective blocks have the identical scanstructures, and a possibility that two blocks having identicalstructures generate identical erroneous output responses because ofhaving identical defects is quite low, if none of the plurality ofblocks has the defect, then the output responses generated by therespective blocks in response to the identical excitation signal shouldbe the same, whereas if one or more blocks have the defect, then theoutput responses of the one or more blocks will be different from thoseof the other blocks. The embodiments of the present disclosure areproposed based on this understanding.

With reference now to FIG. 3, a test apparatus for testing a pluralityof blocks having identical structures according to an embodiment of thepresent disclosure will be described in detail. In the embodiment, thetest apparatus can be included in a chip, for example, be implemented asa circuit in the chip. In another embodiment, the test apparatus may beimplemented as an apparatus or a circuit independent of the chip, whichmay be communicatively connected to the chip and the respective blocks.In a further embodiment, some components (e.g., a comparing device and astorage device described below) of the test apparatus may be placedinside the chip as a part of the chip, and other components of the testapparatus (e.g., a determining device described below) may be placedoutside the chip.

As shown in FIG. 3, the test apparatus 300 may include a comparingdevice 301, a storage device 302 and a determining device 303. The testapparatus 300 is connected to the plurality of blocks having theidentical structures (six blocks 201-206 having the identical structuresin the example shown in FIG. 3).

The comparing device 301 may be connected to an output port of a scanchain of each block, so as to collect, for each test pattern, outputresponses generated by the plurality of blocks by applying an excitationsignal to the plurality of blocks. Then, the comparing device 301 maycompare the output responses of the respective blocks to determinewhether their output responses are identical, and output comparisonresults of the comparing device.

In this embodiment, the comparing device 301 may compare the outputresponses of the plurality of blocks sequentially two by two, todetermine whether the output responses of these blocks are identical. Inthe example shown in FIG. 3, the comparing device 301 may compare outputresponses of blocks 201 and 202, output responses of blocks 202 and 203,output responses of blocks 203 and 204, output responses of blocks 204and 205, and output responses of blocks 205 and 206 sequentially, so asto determine respectively whether the output responses of the two blockswhich are compared are identical. Specifically, the comparing device 301may include a comparing unit provided in the chip for every two blocksto compare the output responses of the two blocks. In oneimplementation, the comparing unit may be implemented by using an XORgate. In another implementation, the comparing unit may be implementedby using other types of integrated or non-integrated comparators orcomparing circuits. In other embodiments, the comparing device 301 maycompare sequentially output responses of three or more blocksrespectively, to determine whether the output responses of these blocksare identical, so as to generate corresponding comparison results. Insuch a case, the comparing device 301 may include one or more comparingunits provided for every three or more blocks. Of course, instead ofproviding a plurality of comparing units, only one comparing unit may beprovided in the comparing device 301 and may be used to perform thecomparing operation described above.

The storage device 302 is connected to the comparing device 301 toreceive the comparison results generated by the comparing device 301 forall of the one or more test patterns and store the comparison results.Specifically, for each test pattern, in a case where the outputresponses of the plurality of blocks are compared sequentially two bytwo, the storage device 302 may store a comparison result generated byeach comparison from the comparing device 301, so as to provide thecomparison result to the determining device 303. For example, if thecomparing device 301 outputs a bit 1 when determining that the outputresponses of two blocks which are compared are different, and outputs abit 0 when determining that the output responses of the two blocks whichare compared are identical, then the storage device 302 may store thebit 0 or 1 generated for every two blocks for indicating whether theoutput responses of the two blocks are identical. The storage device 302may include a storage unit provided in association with each comparingunit (e.g., the XOR gate) and connected to the comparing unit. In oneimplementation, the storage unit may be implemented by an OR gate and aD flip-flop register. In another implementation, the storage unit may beimplemented by another type of small-sized storage device.

After the comparison results generated by the comparing device 301 forall the test patterns are stored in the storage device 302, thecomparison results may be provided from the storage device 302 to thedetermining device 303 for its use. In addition, the comparison resultsmay be output from the storage device 302 serially to outside of thechip, for example, the ATE, via the SO port if necessary for its use. Byserially outputting the comparison results generated for the pluralityof blocks, the number of the SO port of the chip required to be used bythe outputting operation can be reduced, so that the design of the chipmay be simplified.

The determining device 303 may determine whether the plurality of blockshave a defect (e.g., defects corresponding to the respective testpatterns) according to the comparison results. Specifically, for eachtest pattern, in a case where the output responses of the plurality ofblocks are compared sequentially two by two, if the output responses oftwo blocks which are compared are identical, the determining device 303may determine that the two blocks do not have the defect, otherwise maydetermine that at least one of the two blocks has the defect. In a casewhere it is determined that at least one of the two compared blocks hasthe defect, the determining device 303 may further identify the block(s)having the defect according to comparison results between the outputresponses of the two blocks and output responses of other blocks.Specifically, if the output response of one of the two blocks which arecompared is identical to that of another block (i.e., some block in theplurality of blocks having the identical structures other than the twocompared blocks), it can be determined that the other one of the twoblocks has the defect. A method for the determining device 303 toidentify the block having the defect will be described later inconjunction with specific examples.

With reference now to FIG. 4, an exemplary implementation of the testapparatus according to the embodiment of the present disclosure will bedescribed. In this implementation, the test apparatus is implemented asa circuit.

As shown in FIG. 4, an XOR gate (a comparing unit) is provided for everytwo blocks among six blocks 201-206 having identical structures in thecomparing device 301, so that the comparing device 301 includes five XORgates 3011-3015. The XOR gate 3011 receives and compares outputresponses of the blocks 201 and 202, the XOR gate 3012 receives andcompares output responses of the blocks 202 and 203, the XOR gate 3013receives and compares output responses of the blocks 203 and 204, theXOR gate 3014 receives and compares output responses of the blocks 204and 205, and the XOR gate 3015 receives and compares output responses ofthe blocks 205 and 206. If the output response of each block includesonly 1 bit, and the output responses of two blocks compared by each XORgate are different, then the XOR gate outputs 1, otherwise the XOR gateoutputs 0. On the other hand, if the output response of each blockincludes N (N>1) bits, then each XOR gate can compare the outputresponses of the corresponding two blocks bit by bit, and output 1 fordifferent bits and output 0 for identical bits, so as to output thecomparison results for the N bits, and in this case, as long as there isa 1 in the N bits output by the XOR gate, it can be determined that theoutput responses of the two blocks which are compared are different.

In the storage device 302, a storage unit is provided in associationwith each comparing unit, so that the storage device 302 includes fivestorage units 3021-3025. Each storage unit stores a comparison resultoutput from an associated XOR gate. Specifically, as shown in FIG. 4,each storage unit may include an OR gate and a D flip-flop register. TheD flip-flop register can be a scan D flip-flop (SDFF) register which maybe provided with a scan input (SI) port for inputting a scan signal, adata (D) port for inputting data to be registered, a scan output (SO)port for outputting data, a scan enable (SE) port for enabling the SDFFto enter a scan mode, and a clock (CLK) port for inputting a clocksignal. For simplicity, only the D port, the SI port and the SO port aremarked on the SDFF in the storage unit 3021 in FIG. 4 with the otherports being omitted. An input of the OR gate is connected to an outputof the XOR gate, another input of the OR gate is connected to an output(the SO port) of the SDFF, and an output of the OR gate is connected tothe D port of the SDFF, so as to form a feedback loop. In addition, asshown in FIG. 4, a SO port of a SDFF in each storage unit may beconnected to a SI port of a SDFF in an adjacent storage unit, so thatthe SDFFs in the respective storage units form a scan chain, thus, byapplying a driving signal to the SI port of the SDFF in the storage unit3021, comparison results stored in the respective SDFFs can be seriallyoutput to the determining device 303, or to an external device (e.g., anATE) via the SO port of the chip as described above.

Hereinafter, operations of the comparing device 301 and the storagedevice 302 will be described in conjunction with a specific example byusing the comparing unit 3011 and the storage unit 3021 as examples.Since structures and operations of the comparing units 3011-3015 aresimilar to each other, and structures and operations of the storageunits 3021-3025 are similar to each other, the description herein isalso applicable to other comparing units and storage units.

In this example, it is assumed that an expected output responsecorresponding to a test pattern is a 4-digit bit sequence 0100, that is,when an excitation signal corresponding to the test pattern is appliedto each block, a correct output response of the block is the bitsequence 0100, where each time when a clock edge arrives, one bit of thebit sequence is output from the block. If neither of the blocks 201 and202 has a defect corresponding to the test pattern, then their outputresponses are identical (0100), therefore as clock edges arrive, the XORgate 3011 outputs a bit sequence 0000 bit by bit, and the bit sequenceis stored in the SDFF of the storage unit 3021. On the other hand, it isassumed that the block 201 does not have the defect and thus its outputresponse is 0100, while the block 202 has the defect (for example,“stuck-at-1” defect) and thus its output response becomes 0110. In thiscase, when a first clock edge and a second clock edge arrive, since thefirst two bits (01) in the output responses of the two blocks are thesame, the XOR gate 3011 outputs 00, so that 00 are stored in the SDFF.When a third clock edge arrives, since a third bit (0) of the outputresponse of the block 201 is different from a third bit (1) of theoutput response of the block 202, the XOR gate 3011 outputs 1, so that 1is stored in the SDFF. When a fourth clock edge arrives, since fourthbits of the output responses of the blocks 201 and 202 are both 0, theXOR gate 3011 outputs 0, and at this time, since 1 was stored in theSDFF when a previous clock edge arrived, 1 is stored in the SDFF. Thus,for this test pattern, 0011 are stored in the SDFF as a comparisonresult. In the manner described above, a bit sequence indicating aresult of comparison between the output responses of the blocks 201 and202 is stored in the SDFF for each test pattern.

With further reference to FIG. 4, the determining device 303 maydetermine whether the respective blocks have a defect based on thecomparison results stored in the storage device 302 in the mannerdescribed above. The determining device 303 may be implemented as, forexample, an on-chip or off-chip decoding device. Specifically, for acertain test pattern, if the output response of each block has only onebit, so that the comparison result generated by the comparing devicealso have only one bit, then the determining device 303 may determinewhether the respective blocks have the defect corresponding to the testpattern according to the one bit. On the other hand, for a certain testpattern, if the output response of each block includes multiple bits, sothat the comparison result generated by the comparing device alsoincludes multiple bits, then the determining device 303 may check thecomparison result bit by bit, and as long as the block having the defectcorresponding to the test pattern is determined according to one bittherein, the determining device 303 may not check the other bits of thecomparison result any more.

FIG. 5 shows an example of a method for the determining device 303 todetermine the block having the defect in the exemplary case shown inFIG. 4. In FIG. 5, seven blocks 501-507 having identical structures areshown for convenience of explanation, and for the purpose of simplicity,the test apparatus shown in FIG. 3 is not shown, and only the respectiveblocks and the results of the comparison between their output responsestwo by two are shown. Further, it is assumed that for each test pattern,the comparison result generated by the comparing device includes onlyone bit (1 or 0).

In case 1 shown in FIG. 5, the results of the comparison between theoutput responses of the blocks 501-507 two by two are 0, 1, 1, 0, 0, 0respectively for a certain test pattern. In this case, two consecutive 1indicate that there is one block having the defect. Specifically, sincethe output responses of the blocks 502 and 503 are different, it can bedetermined that at least one of the blocks 502 and 503 has the defect.Likewise, since the output responses of the blocks 503 and 504 aredifferent, it can be determined that at least one of the blocks 503 and504 has the defect. Further, since the output responses of the blocks502 and 501 are identical, and the possibility that the two blocks haveidentical defects and thus generate identical erroneous output responsesis quite low, it can be determined that the blocks 501 and 502 do nothave the defect, thereby it can be determined that the block 503 has thedefect. Likewise, since the output responses of the blocks 504 and 505are identical, it can be determined that the block 504 does not have thedefect, thereby it can also be determined that the block 503 has thedefect.

In case 2 shown in FIG. 5, the results of the comparison between theoutput responses of the blocks 501-507 two by two are 0, 1, 1, 0, 1, 1respectively for a certain test pattern, i.e., there are two groups oftwo consecutive 1, which indicate that two of the blocks 501-507 havethe defect. In this case, it can be determined that the blocks 503 and506 have the defect in a manner similar to that for case 1.

In case 3 shown in FIG. 5, the results of the comparison between theoutput responses of the blocks 501-507 two by two are 0, 1, 1, 1, 0, 0respectively for a certain test pattern, i.e., there are threesuccessive 1. In this case, it can be determined that at least one ofthe blocks 502 and 503, at least one of the blocks 503 and 504, and atleast one of the blocks 504 and 505 have the defect in the mannerdescribed above. Further, since the output responses of the blocks 502and 501 are the same, it can be determined that the block 502 does nothave the defect, thereby it can be determined that the block 503 has thedefect. Likewise, it can be determined that the block 506 does not havethe defect, and the block 505 has the defect. As for the block 504, itsoutput response is different from the output responses of the blocks 503and 505 having the defect, so it can not be determined that the block504 has the defect. In this case, the block 504 may be considered ashaving the defect from a viewpoint of ensuring a normal operation of thecircuit as far as possible.

With the above test apparatus according to the embodiment of the presentdisclosure, the plurality of blocks having the identical structures canbe tested in parallel, so the test efficiency can be improved, and themore the blocks having the identical structures in the chip are, thehigher the test efficiency is. Further, since the plurality of blockscan share one or more test patterns, the test process can be simplified.In addition, the test apparatus can be wholly or partially disposed onthe chip, so that the test on the chip is more efficient. Moreover,since the test apparatus can be implemented by using a simple circuit, acost and a size of the chip can be reduced.

It is to be recognized that the above embodiments are only illustrativerather than limitative. When necessary, those skilled in the art canmake various changes to the above embodiments. For example, although itis mentioned in the above that the test apparatus includes the storagedevice 302, the storage device may be omitted, in which case thedetermining device 303 may directly receive the comparison resultsgenerated by the comparing device 301, and determine the block havingthe defect instantly in the manner described above, for example.Furthermore, the embodiment of the present disclosure is described aboveby taking connection of the scan registers in each block into one scanchain as an example, but this is not limitative, and the scan registersin each block may also be connected into a plurality of scan chains, andthe respective blocks have identical scan structures, in which caseoutput responses of corresponding scan chains (e.g., in a case where thescan chains in the respective blocks are numbered respectively in thesame order, the scan chains having the same numbers in the respectiveblocks are the corresponding scan chains) in the respective blocks maybe compared, and the blocks having the defect is determined in the abovemanner. Therefore, the test apparatus according to the embodiment of thepresent disclosure may have a flexible structure, and thereby may adoptdifferent structures according to different chips.

With reference now to FIG. 6, a test method for testing a plurality ofblocks in a circuit according to an embodiment of the present disclosurewill be described below. Because the test method and the test apparatusdescribed above are based on the same inventive concept, same orcorresponding implementation details mentioned when the test apparatusis described are also applicable to the test method corresponding to thetest apparatus described above, and since the test apparatus has beendescribed in detail above, descriptions of the details may be omittedhereinafter. Here, the description is still made by taking a chip as anexample of the circuit. In addition, as described above, the pluralityof blocks have identical scan chains, each of which includes at leastone scan register, and input ports of the scan chains of the respectiveblocks are connected together, so that an excitation signalcorresponding to each test pattern can be applied to the scan chains ofthe plurality of blocks in parallel.

As shown in FIG. 6, in step S601, output responses generated by theplurality of blocks by applying a corresponding excitation signal to theplurality of blocks may be collected.

Then, in step S602, the output responses of the respective blocks may becompared, to determine whether the output responses of the respectiveblocks are identical. In this embodiment, the output responses of theplurality of blocks may be compared sequentially two by two, todetermine whether the output responses of these blocks are identical.For example, the output responses of every two blocks may be compared bya comparing unit provided in the chip for the two blocks. In oneimplementation, the comparing unit may be implemented by using an XORgate. In another implementation, the comparing unit may be implementedby using other type of integrated or non-integrated comparator orcomparing circuit. In other embodiments, the output responses of threeor more blocks may be respectively compared sequentially, to determinewhether the output responses of these blocks are identical, so as togenerate corresponding comparison results.

For each test pattern, after the output responses of the plurality ofblocks are compared sequentially two by two and thereby the comparisonresults are generated, the comparison results may be stored. Forexample, the comparison results may be stored by a storage device. Thestorage device may include a storage unit provided in association witheach comparing unit (e.g., the XOR gate) and connected to the comparingunit. In one implementation, the storage unit may be implemented by anOR gate and a D flip-flop register, where, as shown in FIG. 4, an inputof the OR gate is connected to an output of the associated XOR gate,another input of the OR gate is connected to an output of the Dflip-flop register, and an output of the OR gate is connected to aninput of the D flip-flop register. In other implementations, the storageunit may be implemented by other type of small-sized storage device.

With further reference to FIG. 6, in step S603, it may be determinedwhether the plurality of blocks have a defect (e.g., defectscorresponding to the respective test patterns) according to thecomparison results. Specifically, for each test pattern, in a case wherethe output responses of the plurality of blocks are comparedsequentially two by two, if the output responses of two blocks which arecompared are identical, it may be determined that the two blocks do nothave the defect; otherwise, it may be determined that at least one ofthe two blocks has the defect. In a case where it is determined that atleast one of the two blocks which are compared has the defect, the blockhaving the defect may be further identified according to results ofcomparisons between the output responses of the two blocks and theoutput responses of other blocks. Specifically, if the output responseof one of the two blocks which are compared is identical to the outputresponse of another block (i.e., some block in the plurality of blockshaving the identical structures other than the two compared blocks), itcan be determined that the other one of the two blocks has the defect.

Thus, with the test method according to the embodiment of the presentdisclosure described above, the plurality of blocks having the identicalstructures can be tested in parallel, which can significantly improvetest efficiency in a case where the chip has many blocks havingidentical structures. Furthermore, since the plurality of blocks canshare one or more test patterns, the test process can be simplified.

Various embodiments for implementing the test apparatus and the testmethod according to the embodiments of the present disclosure have beendescribed above with reference to the accompanying drawings. Thoseskilled in the art may understand that these embodiments are onlyexemplary rather than limitative. For example, although the testapparatus is implemented as a circuit in the above, the test apparatusdescribed above can actually be implemented by software, hardware, or acombination thereof. For example, the test apparatus according to theembodiment of the present disclosure may be implemented by theabove-described exemplary computer system/server in combination with thesoftware. In this case, even if the exemplary computer system/server isthe same as a general-purpose processing apparatus in hardwareconfiguration, the apparatus will exhibit characteristics different fromthe general-purpose processing apparatus due to the function of thesoftware contained therein, thereby forming the test apparatus accordingto the embodiment of the present disclosure. The apparatus of thepresent disclosure comprises a plurality of units or blocks which areconfigured to execute corresponding steps. Those skilled in the art mayunderstand how to write a program to implement actions performed by theunits or blocks by reading the present specification.

For example, FIG. 7 shows a test apparatus for testing a plurality ofblocks having identical structures in a circuit according to anotherembodiment of the present disclosure. The test apparatus can perform thetest method described above. As shown in FIG. 7, the test apparatuscomprises a collecting device 701, a comparing device 702, a storagedevice 703 and a determining device 704. In some embodiments, thestorage device 703 may be omitted. Operation details of these blocks arethe same as those described above with respect to the test apparatus 300and the test method according to the embodiments of the presentdisclosure, so the operations of the respective blocks are onlydescribed briefly below, and descriptions of the same details areomitted.

The collecting device 701 may collect output responses generated by theplurality of blocks by applying a corresponding excitation signal to theplurality of blocks.

The comparing device 702 may compare the output responses of therespective blocks, to determine whether the output responses of therespective blocks are identical. In this embodiment, the comparingdevice 702 may compare the output responses of the plurality of blockssequentially two by two, to determine whether the output responses ofthese blocks are identical. For example, the comparing device 702 maycompare the output responses of every two blocks by a comparing unitprovided in the chip for the two blocks. In other embodiments, thecomparing device 702 may sequentially compare the output responses ofthree or more blocks respectively, to determine whether the outputresponses of these blocks are identical, so as to generate correspondingcomparison results.

The storage device 703 may store the comparison results of the comparingdevice 702. Specifically, for each test pattern, after the outputresponses of the plurality of blocks are compared sequentially two bytwo and thereby the comparison results are generated, the storage device703 may store the comparison results. The storage device 703 may includea storage unit provided in association with each comparing unit andconnected to the comparing unit.

The determining device 704 may determine whether the plurality of blockshave a defect (e.g., defects corresponding to the respective testpatterns) according to the comparison results. Specifically, for eachtest pattern, in a case where the output responses of the plurality ofblocks are compared sequentially two by two, if the output responses oftwo blocks which are compared are identical, the determining device 704may determine that the two blocks do not have the defect, otherwise thedetermining device 704 may determine that at least one of the two blockshas the defect. In a case where it is determined that at least one ofthe two compared blocks has the defect, the determining device 704 mayfurther identify the block having the defect according to results ofcomparisons between the output responses of the two blocks and theoutput responses of other blocks. Specifically, if the output responsesof one of the two compared blocks are identical to the output responseof another block (i.e., some block in the plurality of blocks having theidentical structures other than the two compared blocks), thedetermining device 704 may determine that the other one of the twoblocks has the defect.

Thus, with the test apparatus according to the embodiment of the presentdisclosure described above, in a case where the chip has many blockshaving identical structures, the test process can be simplified and thetest efficiency can be improved.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A test apparatus for testing a plurality ofblocks in a circuit, the plurality of blocks having identicalstructures, the test apparatus comprising: a comparing device,configured to collect output responses generated by the plurality ofblocks by applying an excitation signal to the plurality of blocks inparallel, compare the output responses of the plurality of blocks todetermine whether the output responses of the plurality of blocks areidentical, and output results of the comparison of the comparing device,wherein the comparing device compares the output responses of theplurality of blocks sequentially two by two to determine whether theoutput responses of the plurality of blocks are identical; and adetermining device, configured to receive the results of the comparisonof the comparing device, and determine whether the plurality of blockshave a defect according to the results of the comparison of thecomparing device.
 2. The test apparatus of claim 1, wherein in responseto the output responses of two blocks under comparison being identical,the determining device determines that neither of the two blocks undercomparison have the defect.
 3. The test apparatus of claim 1, wherein inresponse to the output responses of two blocks under comparison beingdifferent, the determining device determines that at least one of thetwo blocks under comparison has the defect.
 4. The test apparatus ofclaim 1, wherein in response to the output responses of two blocks undercomparison being different, and the output response of one of the twoblocks under comparison being identical to an output response of anotherblock in the plurality of blocks other than the two blocks undercomparison, the determining device determines that the other one of thetwo blocks under comparison has the defect.
 5. The test apparatus ofclaim 1, wherein the plurality of blocks include scan chains havingidentical structures, each scan chain including at least one scanregister, and wherein the excitation signal is applied to the scanchains of the plurality of blocks in parallel.
 6. The test apparatus ofclaim 1, wherein the comparing device includes an XOR gate provided inthe circuit for every two blocks, for comparing the output responses ofthe two blocks.
 7. The test apparatus of claim 6, further comprising: astorage device, configured to store the results of the comparisongenerated by comparing the output responses of the plurality of blockssequentially two by two, so as to provide the results of the comparisonto the determining device.
 8. The test apparatus of claim 7, wherein thestorage device includes an OR gate and a D flip-flop register providedin association with each XOR gate, an input of the OR gate beingconnected to an output of the associated XOR gate, another input of theOR gate being connected to an output of the D flip-flop register, anoutput of the OR gate being connected to an input of the D flip-flopregister, and the output of the D flip-flop register being connected toan input of another D flip-flop register associated with another XORgate.
 9. The test apparatus of claim 1, wherein the test apparatus isincluded in the circuit.
 10. A test method for testing a plurality ofblocks in a circuit, the plurality of blocks having identicalstructures, the test method comprising: collecting output responsesgenerated by the plurality of blocks by applying an excitation signal tothe plurality of blocks in parallel; comparing the output responses ofthe plurality of blocks sequentially two by two, to determine whetherthe output responses of the plurality of blocks are identical.
 11. Thetest method of claim 10, in response to the output responses of twoblocks under comparison being identical, determining that neither of thetwo blocks under comparison have a defect.
 12. The test method of claim10, in response to the output responses of two blocks under comparisonbeing different, determining that at least one of the two blocks undercomparison has the defect.
 13. The test method of claim 10, in responseto the output responses of the two blocks under comparison beingdifferent, and the output response of one of the two blocks undercomparison being identical to an output response of another block in theplurality of blocks other than the two blocks under comparison,determining that the other one of the two blocks under comparison hasthe defect.
 14. The test method of claim 10, wherein the plurality ofblocks include scan chains having identical structures, each scan chainincluding at least one scan register, and wherein the excitation signalis applied to the scan chains of the plurality of blocks in parallel.15. The test method of claim 10, wherein an XOR gate provided for everytwo blocks is used for comparing the output responses of the two blocks.16. The test method of claim 15, further comprising: storing the resultsof the comparison generated by comparing the output responses of theplurality of blocks sequentially two by two, for use in determiningwhether the plurality of blocks have the defect.
 17. The test method ofclaim 16, wherein the results of the comparison are stored by a storagedevice including an OR gate and a D flip-flop register provided inassociation with each XOR gate, an input of the OR gate being connectedto an output of the associated XOR gate, another input of the OR gatebeing connected to an output of the D flip-flop register, an output ofthe OR gate being connected to an input of the D flip-flop register, andthe output of the D flip-flop register being connected to an input ofanother D flip-flop register associated with another XOR gate.